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捕获设置
1.设置0的8位捕获功能（PB0）：高电平脉宽捕获、上升沿开始捕获，下降沿产生中断
clr P_IOB_Data,0
clr P_IOB_Attrib,0
clr P_IOB_Dir,0 ;Set PB0 as input pull low for CAP0
lda #$0
sta P_TMR0_Preload ;Set Timer0 preload counter= 0
lda P_TMR0_1_Ctrl1
and #$F0
ora #C_T0FCS_Div_512
sta P_TMR0_1_Ctrl1 ;Set Timer0 clock source is Fsys(8000000)/512=15.6KHz
lda P_TMR0_1_Ctrl0
and #$F0
ora #C_T08B_CAP
sta P_TMR0_1_Ctrl0 ;Set Timer0 is 8-bit capture
clr P_CAP_Ctrl, CB_CAP0_ES
;rising edge sample data
clr P_CAP_Ctrl,CB_CAP_IP0
;CAP0 int edge opposite to sample edge
set P_INT_Flag1,CB_INT_CAP0IF
;clear int flag
set P_INT_Ctrl1,CB_INT_CAP0IE
;set cap0 INT
cli
;read idth capture result from P_TMR0_Cap
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2. 设置Timer0的8位捕获功能（PB0）：低电平脉宽捕获、下降沿开始捕获，上升沿产生中断
clr P_IOB_Data,0
clr P_IOB_Attrib,0
clr P_IOB_Dir,0 ;Set PB0 as input pull low for CAP0
lda #$0
sta P_TMR0_Preload ;Set Timer0 preload counter= 0
lda P_TMR0_1_Ctrl1
and #$F0
ora #C_T0FCS_Div_512
sta P_TMR0_1_Ctrl1 ;Set Timer0 clock source is Fsys(8000000)/512=15.6KHz
lda P_TMR0_1_Ctrl0
and #$F0
ora #C_T08B_CAP
sta P_TMR0_1_Ctrl0 ;Set Timer0 is 8-bit capture
set P_CAP_Ctrl,CB_CAP0_ES
; falling edge sample data
clr P_CAP_Ctrl,CB_CAP_IP0
;CAP0 int edge opposite to sample edge
set P_INT_Flag1,CB_INT_CAP0IF
;clear int flag
set P_INT_Ctrl1,CB_INT_CAP0IE
;set cap0 INT
cli
;read Width capture result from P_TMR0_Cap
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3. 设置Timer1的8位捕获功能（PB1）：高电平脉宽捕获、上升沿开始捕获，下降沿产生中断
clr P_IOB_Data,1
clr P_IOB_Attrib,1
clr P_IOB_Dir,1 ;Set PB1 as input pull low for cap1
lda #$0
sta P_TMR1_Preload ;Set Timer1 preload counter= 0
lda P_TMR0_1_Ctrl1
and #$0F
ora #C_T1FCS_Div_512
sta P_TMR0_1_Ctrl1 ;Set Timer1 clock source is Fsys(8000000)/512=15.6KHz
lda P_TMR0_1_Ctrl0
and #$0F
ora #C_T18B_CAP
sta P_TMR0_1_Ctrl0 ;Set Timer1 is 8-bit capture
clr P_CAP_Ctrl,CB_CAP1_ES
;rising edge sample data
clr P_CAP_Ctrl,CB_CAP_IP1
;cap1 int edge opposite to sample edge
set P_INT_Flag1,CB_INT_CAP1IF
;clear int flag
set P_INT_Ctrl1,CB_INT_CAP1IE
;set cap1 INT
cli
; read Width capture result from P_TMR1_Cap
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4. 设置Timer1的8位捕获功能（PB1）：低电平脉宽捕获、下降沿开始捕获，上升沿产生中断
clr P_IOB_Data,1
clr P_IOB_Attrib,1
clr P_IOB_Dir,1 ;Set PB1 as input pull low for CAP1
lda #$0
sta P_TMR1_Preload ;Set Timer1 preload counter= 0
lda P_TMR0_1_Ctrl1
and #$0F
ora #C_T1FCS_Div_512
sta P_TMR0_1_Ctrl1 ;Set Timer1 clock source is Fsys(8000000)/512=15.6KHz
lda P_TMR0_1_Ctrl0
and #$0F
ora #C_T18B_CAP
sta P_TMR0_1_Ctrl0 ;Set Timer1 is 8-bit capture
set P_CAP_Ctrl,CB_CAP1_ES
;falling edge sample data
clr P_CAP_Ctrl,CB_CAP_IP1
;CAP1 int edge opposite to sample edge
set P_INT_Flag1,CB_INT_CAP1IF
;clear int flag
set P_INT_Ctrl1,CB_INT_CAP1IE
;set cap1 INT
cli
; read Width capture result from P_TMR1_Cap |
5. 设置Timer1的8位捕获功能（PB1）：周期捕获、上升沿开始捕获，上升沿产生中断
clr P_IOB_Data,1
clr P_IOB_Attrib,1
clr P_IOB_Dir,1 ;Set PB1 as input pull low for CAP1
lda #$0
sta P_TMR1_Preload ;Set Timer1 preload counter= 0
lda P_TMR0_1_Ctrl1
and #$0F
ora #C_T1FCS_Div_512
sta P_TMR0_1_Ctrl1 ;Set Timer1 clock source is Fsys(8000000)/512=15.6KHz
lda P_TMR0_1_Ctrl0
and #$0F
ora #C_T18B_CAP
sta P_TMR0_1_Ctrl0 ;Set Timer1 is 8-bit capture
clr P_CAP_Ctrl, CB_CAP1_ES
;rising edge sample data
set P_CAP_Ctrl,CB_CAP_IP1
; cap1 int edge same with sample edge
set P_INT_Flag1 ,CB_INT_CAP1IF
;clear int flag
set P_INT_Ctrl1, CB_INT_CAP1IE
;set cap1 INT
cli
; read Width capture result from P_TMR1_Cap
; read Period result from P_TMR1_CapHi |
6. 设置Timer1的8位捕获功能（PB1）：周期捕获、下降沿开始捕获，下降沿产生中断
clr P_IOB_Data,1
clr P_IOB_Attrib,1
clr P_IOB_Dir,1 ;Set PB1 as input pull low for CAP1
lda #$0
sta P_TMR1_Preload ;Set Timer1 preload counter= 0
lda P_TMR0_1_Ctrl1
and #$0F
ora #C_T1FCS_Div_512
sta P_TMR0_1_Ctrl1 ;Set Timer1 clock source is Fsys(8000000)/512=15.6KHz
lda P_TMR0_1_Ctrl0
and #$0F
ora #C_T18B_CAP
sta P_TMR0_1_Ctrl0 ;Set Timer1 is 8-bit capture
set P_CAP_Ctrl,CB_CAP1_ES
;falling edge sample data
set P_CAP_Ctrl,CB_CAP_IP1
;CAP1 int edge same with sample edge
set P_INT_Flag1,CB_INT_CAP1IF
;clear int flag
set P_INT_Ctrl1,CB_INT_CAP1IE
;set cap1 INT
cli
; read Period result from P_TMR1_CapHi and P_TMR1_Cap |
7. 设置Timer1的16位捕获功能（PB1）：高电平脉宽捕获、上升沿开始捕获，下降沿产生中断
clr P_IOB_Data,1
clr P_IOB_Attrib,1
clr P_IOB_Dir,1 ;Set PB1 as input pull low for CAP1
lda #$0
sta P_TMR1_Preload ;Set Timer1 preload counter= 0
lda P_TMR0_1_Ctrl1
and #$0F
ora #C_T1FCS_Div_512
sta P_TMR0_1_Ctrl1 ;Set Timer1 clock source is Fsys(8000000)/512=15.6KHz
lda P_TMR0_1_Ctrl0
and #$0F
ora #C_T116B_CAP
sta P_TMR0_1_Ctrl0 ;Set Timer1 is 16-bit capture
clr P_CAP_Ctrl,CB_CAP1_ES
;rising edge sample data
clr P_CAP_Ctrl,CB_CAP_IP1
;CAP1 int edge opposite to sample edge
set P_INT_Flag1,CB_INT_CAP1IF
;clear int flag
set P_INT_Ctrl1,CB_INT_CAP1IE
;set cap1 INT
cli
; read Period result from P_TMR1_CapHi and P_TMR1_Cap |
8. 设置Timer1的16位捕获功能（PB1）：低电平脉宽捕获、下降沿开始捕获，上升沿产生中断
clr P_IOB_Data,1
clr P_IOB_Attrib,1
clr P_IOB_Dir,1 ;Set PB1 as input pull low for CAP1
lda #$0
sta P_TMR1_Preload ;Set Timer1 preload counter= 0
lda P_TMR0_1_Ctrl1
and #$0F
ora #C_T1FCS_Div_512
sta P_TMR0_1_Ctrl1 ;Set Timer1 clock source is Fsys(8000000)/512=15.6KHz
lda P_TMR0_1_Ctrl0
and #$0F
ora #C_T116B_CAP
sta P_TMR0_1_Ctrl0 ;Set Timer1 is 16-bit capture
set P_CAP_Ctrl,CB_CAP1_ES
;falling edge sample data
clr P_CAP_Ctrl,CB_CAP_IP1
;CAP int edge opposite to sample edge
set P_INT_Flag1,CB_INT_CAP1IF
;clear int flag
set P_INT_Ctrl1,CB_INT_CAP1IE
;set cap1 INT
cli
; read Period result from P_TMR1_CapHi and P_TMR1_Cap |
9. 设置Timer2的8位捕获功能（PB4）：高电平脉宽捕获、上升沿开始捕获，下降沿产生中断
clr P_IOB_Data,4
clr P_IOB_Attrib,4
clr P_IOB_Dir,4 ;Set PB4 as input pull low for CAP2
lda #$0
sta P_TMR2_Preload ;Set Timer2 preload counter= 0
lda P_TMR2_3_Ctrl1
and #$F0
ora #C_T2FCS_Div_512
sta P_TMR2_3_Ctrl1 ;Set Timer2 clock source is Fsys(8000000)/512=15.6KHz
lda P_TMR2_3_Ctrl0
and #$F0
ora #C_T28B_CAP
sta P_TMR2_3_Ctrl0 ;Set Timer2 is 8-bit capture
clr P_IRQ_Opt1,CB_IRQOpt1_CAP2ES
clr P_IRQ_Opt1,CB_IRQOpt1_CAP2ES
;rising edge sample data
clr P_CAP_Ctrl,CB_CAP_IP2
;CAP2 int edge opposite to sample edge
set P_INT_Flag0,CB_INT_CAP2IF
;clear int flag
set P_INT_Ctrl0,CB_INT_CAP2IE
;set cap2 INT
cli
;read Width capture result from P_TMR2_Cap |
10. 设置Timer2的8位捕获功能（PB4）：低电平脉宽捕获、下降沿开始捕获，上升沿产生中断
clr P_IOB_Data,4
clr P_IOB_Attrib,4
clr P_IOB_Dir,4 ;Set PB4 as input pull low for CAP2
lda #$0
sta P_TMR2_Preload ;Set Timer2 preload counter= 0
lda P_TMR2_3_Ctrl1
and #$F0
ora #C_T2FCS_Div_512
sta P_TMR2_3_Ctrl1 ;Set Timer2 clock source is Fsys(8000000)/512=15.6KHz
lda P_TMR2_3_Ctrl0
and #$F0
ora #C_T28B_CAP
sta P_TMR2_3_Ctrl0 ;Set Timer2 is 8-bit capture
set P_IRQ_Opt1,CB_IRQOpt1_CAP2ES
set P_IRQ_Opt1,CB_IRQOpt1_CAP2ES
;falling edge sample data,need write twice
clr P_CAP_Ctrl,CB_CAP_IP2
;CAP2 int edge opposite to sample edge
set P_INT_Flag0,CB_INT_CAP2IF
;clear int flag
set P_INT_Ctrl0,CB_INT_CAP2IE
;set cap2 INT
cli
;read Width capture result from P_TMR2_Cap |
11. 设置Timer3的8位捕获功能（PB5）：高电平脉宽捕获、上升沿开始捕获，下降沿产生中断
clr P_IOB_Data,5
clr P_IOB_Attrib,5
clr P_IOB_Dir,5 ;Set PB5 as input pull low for cap3
lda #$0
sta P_TMR3_Preload ;Set Timer3 preload counter= 0
lda P_TMR2_3_Ctrl1
and #$0F
ora #C_T3FCS_Div_512
sta P_TMR2_3_Ctrl1 ;Set Timer3 clock source is Fsys(8000000)/512=15.6KHz
lda P_TMR2_3_Ctrl0
and #$0F
ora #C_T38B_CAP
sta P_TMR2_3_Ctrl0 ;Set Timer3 is 8-bit capture
clr P_IRQ_Opt1,CB_IRQOpt1_CAP3ES
clr P_IRQ_Opt1,CB_IRQOpt1_CAP3ES
;rising edge sample data
clr P_CAP_Ctrl,CB_CAP_IP3
;cap3 int edge opposite to sample edge
set P_INT_Flag0,CB_INT_CAP3IF
;clear int flag
set P_INT_Ctrl0,CB_INT_CAP3IE
;set cap3 INT
cli
; read Width capture result from P_TMR3_Cap
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12. 设置Timer3的8位捕获功能（PB5）：低电平脉宽捕获、下降沿开始捕获，上升沿产生中断
clr P_IOB_Data,5
clr P_IOB_Attrib,5
clr P_IOB_Dir,5 ;Set PB5 as input pull low for cap3
lda #$0
sta P_TMR3_Preload ;Set Timer3 preload counter= 0
lda P_TMR2_3_Ctrl1
and #$0F
ora #C_T3FCS_Div_512
sta P_TMR2_3_Ctrl1 ;Set Timer3 clock source is Fsys(8000000)/512=15.6KHz
lda P_TMR2_3_Ctrl0
and #$0F
ora #C_T38B_CAP
sta P_TMR2_3_Ctrl0 ;Set Timer3 is 8-bit capture
set P_IRQ_Opt1,CB_IRQOpt1_CAP3ES
set P_IRQ_Opt1,CB_IRQOpt1_CAP3ES
;falling edge sample data
clr P_CAP_Ctrl,CB_CAP_IP3
;cap3 int edge opposite to sample edge
set P_INT_Flag0,CB_INT_CAP3IF
;clear int flag
set P_INT_Ctrl0,CB_INT_CAP3IE
;set cap3 INT
cli
; read Width capture result from P_TMR3_Cap |
13. 设置Timer3的8位捕获功能（PB5）：周期和脉宽捕获、下降沿开始捕获，下降沿产生中断
clr P_IOB_Data,5
clr P_IOB_Attrib,5
clr P_IOB_Dir,5 ;Set PB5 as input pull low for cap3
lda #$0
sta P_TMR3_Preload ;Set Timer3 preload counter= 0
lda P_TMR2_3_Ctrl1
and #$0F
ora #C_T3FCS_Div_512
sta P_TMR2_3_Ctrl1 ;Set Timer3 clock source is Fsys(8000000)/512=15.6KHz
lda P_TMR2_3_Ctrl0
and #$0F
ora #C_T38B_CAP
sta P_TMR2_3_Ctrl0 ;Set Timer3 is 8-bit capture
set P_IRQ_Opt1,CB_IRQOpt1_CAP3ES
set P_IRQ_Opt1,CB_IRQOpt1_CAP3ES
;falling edge sample data
set P_CAP_Ctrl,CB_CAP_IP3
;cap3 int edge same with sample edge
set P_INT_Flag0,CB_INT_CAP3IF
;clear int flag
set P_INT_Ctrl0,CB_INT_CAP3IE
;set cap3 INT
cli
; read Width capture result from P_TMR3_Cap
; read Period result from P_TMR3_CapHi |
14. 设置Timer3的8位捕获功能（PB5）：周期和脉宽捕获、上升沿开始捕获，上升沿产生中断
clr P_IOB_Data,5
clr P_IOB_Attrib,5
clr P_IOB_Dir,5 ;Set PB5 as input pull low for cap3
lda #$0
sta P_TMR3_Preload ;Set Timer3 preload counter= 0
lda P_TMR2_3_Ctrl1
and #$0F
ora #C_T3FCS_Div_512
sta P_TMR2_3_Ctrl1 ;Set Timer3 clock source is Fsys(8000000)/512=15.6KHz
lda P_TMR2_3_Ctrl0
and #$0F
ora #C_T38B_CAP
sta P_TMR2_3_Ctrl0 ;Set Timer3 is 8-bit capture
clr P_IRQ_Opt1,CB_IRQOpt1_CAP3ES
clr P_IRQ_Opt1,CB_IRQOpt1_CAP3ES
;rising edge sample data
set P_CAP_Ctrl,CB_CAP_IP3
;cap3 int edge same with sample edge
set P_INT_Flag0,CB_INT_CAP3IF
;clear int flag
set P_INT_Ctrl0,CB_INT_CAP3IE
;set cap3 INT
cli
; read Width capture result from P_TMR3_Cap
; read Period result from P_TMR3_CapHi |
15. 设置Timer3的16位捕获功能（PB5）：高电平脉宽捕获、上升沿开始捕获，下降沿产生中断
clr P_IOB_Data,5
clr P_IOB_Attrib,5
clr P_IOB_Dir,5 ;Set PB5 as input pull low for cap3
lda #$0
sta P_TMR3_Preload ;Set Timer3 preload counter= 0
lda P_TMR2_3_Ctrl1
and #$0F
ora #C_T3FCS_Div_512
sta P_TMR2_3_Ctrl1 ;Set Timer3 clock source is Fsys(8000000)/512=15.6KHz
lda P_TMR2_3_Ctrl0
and #$0F
ora #C_T316B_CAP
sta P_TMR2_3_Ctrl0 ;Set Timer3 is 16-bit capture
clr P_IRQ_Opt1,CB_IRQOpt1_CAP3ES
clr P_IRQ_Opt1,CB_IRQOpt1_CAP3ES
;rising edge sample data
clr P_CAP_Ctrl,CB_CAP_IP3
;cap3 int edge opposite to sample edge
set P_INT_Flag0,CB_INT_CAP3IF
;clear int flag
set P_INT_Ctrl0,CB_INT_CAP3IE
;set cap3 INT
cli
; read Period result from P_TMR3_CapHi and P_TMR3_Cap |
16. 设置Timer3的16位捕获功能（PB5）：低电平脉宽捕获、下降沿开始捕获，上升沿产生中断
clr P_IOB_Data,5
clr P_IOB_Attrib,5
clr P_IOB_Dir,5 ;Set PB5 as input pull low for cap3
lda #$0
sta P_TMR3_Preload ;Set Timer3 preload counter= 0
lda P_TMR2_3_Ctrl1
and #$0F
ora #C_T3FCS_Div_512
sta P_TMR2_3_Ctrl1 ;Set Timer3 clock source is Fsys(8000000)/512=15.6KHz
lda P_TMR2_3_Ctrl0
and #$0F
ora #C_T316B_CAP
sta P_TMR2_3_Ctrl0 ;Set Timer3 is 16-bit capture
set P_IRQ_Opt1,CB_IRQOpt1_CAP3ES
set P_IRQ_Opt1,CB_IRQOpt1_CAP3ES
;falling edge sample data
clr P_CAP_Ctrl,CB_CAP_IP3
;cap3 int edge opposite to sample edge
set P_INT_Flag0,CB_INT_CAP3IF
;clear int flag
set P_INT_Ctrl0,CB_INT_CAP3IE
;set cap3 INT
cli
; read Period result from P_TMR3_CapHi and P_TMR3_Cap |
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